Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in the minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Among the efforts for resolving the above-discussed limitations, three-dimensional integrated circuit (3DIC) and stacked dies are commonly used. Through-silicon vias (TSVs) are often used in 3DICs and stacked dies for connecting dies. In this case, TSVs are used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide a short grounding path to connect the ground in the integrated circuits to the backside of the die, which is typically covered by a grounded aluminum film.
FIG. 1 illustrates a conventional integrated circuit structure, which includes semiconductor chip 100 and TSV 112 formed therein. Semiconductor chip 100 includes substrate 110, on which integrated circuits (not shown) are formed. Interconnect structure 116 is formed over substrate 110, and includes a plurality of metallization layers having metal lines and vias (not shown) formed in dielectric layers (commonly referred to as inter-metal dielectrics). Passivation layer 118 (often referred to as passivation-1) is formed on a top metallization layer. Aluminum pad 122 is formed on passivation layer 118 and is connected to the metal lines in interconnect structure 116. Passivation layer 120 (often referred to as passivation-2) is formed on passivation layer 118. An opening is formed in passivation layer 120 to expose aluminum pad 122. TSV 112 is electrically connected to aluminum pad 122 through copper line 124. Isolation layer 126 is formed to isolate TSV 112 from substrate 110, wherein isolation layer 126 extends over the top surface of passivation layer 120. Through this structure, TSV 112 is electrically connected to the integrated circuits in semiconductor chip 100.
The structure shown in FIG. 1 suffers from drawbacks. The formation of passivation layers 118 and 120 are inherited from legacy processes. The stacking of passivation layer 118, 120, and insulation layer 126 not only involves more complicated manufacturing processes, but the resistance of aluminum pad 122 and the contact resistance between aluminum pad 122 and its adjoining metal features further causes the increase in RC delay. In addition, the material difference at the interface between aluminum pad 122 and overlying copper line 124 may cause delamination. Accordingly, new TSV formation processes are needed to form more reliable TSV structures without increasing the manufacturing cost.